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Disambiguation of "Chaivipas, Win"

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A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process.

, , , , , , , , , , and . J. Solid-State Circuits, 48 (12): 3258-3267 (2013)

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Hon. -Prof. Dr. -Ing. Stefan Winkler University of Stuttgart

Marius Winter University of Stuttgart

Jonas Winkler University of Stuttgart

Daniel Winkle University of Stuttgart

Matthias Winkler University of Stuttgart

 

Other publications of authors with the same name

Analysis of CMOS Transconductance Amplifiers for Sampling Mixers., , , and . IEICE Transactions, 91-C (6): 871-878 (2008)A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter., , and . IEICE Transactions, 90-C (6): 1311-1314 (2007)Feedforward compensation technique for all digital phase locked loop based synthesizers., , and . ISCAS, IEEE, (2006)A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c., , , , , , , , , and 3 other author(s). ISSCC, page 160-162. IEEE, (2011)A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications., , , , , and . J. Solid-State Circuits, 46 (11): 2635-2649 (2011)Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators., , and . IEICE Transactions, 91-C (6): 918-927 (2008)A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (12): 3258-3267 (2013)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS., , , , , , , , , and . ASP-DAC, page 467-468. IEEE, (2012)