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Disambiguation of "Mori, Toshihiko"

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22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS.

, , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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Dr. -Ing. Stephanie Moritz University of Stuttgart

Anke Moritz University of Stuttgart

 

Other publications of authors with the same name

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets., , , , , , , , , and 10 other author(s). ISSCC, page 86-88. IEEE, (2012)Neural-network assistance to calculate precise eigenvalue for fitness evaluation of real product design., , , , , , and . GECCO (Companion), page 405-406. ACM, (2019)Non-binary SAR ADC with digital error correction for low power applications., , , , , , , , and . APCCAS, page 196-199. IEEE, (2010)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 64-65. IEEE, (2016)A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing., , , and . ISSCC, page 452-614. IEEE, (2007)22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 49 (12): 2915-2924 (2014)A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications., , , , and . ESSCIRC, page 349-352. IEEE, (2012)SAR ADC Algorithm with Redundancy and Digital Error Correction., , , , , , , , , and . IEICE Transactions, 93-A (2): 415-423 (2010)