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Disambiguation of "Kobayashi, Haruo"

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SAR ADC Algorithm with Redundancy and Digital Error Correction.

, , , , , , , , , and . IEICE Transactions, 93-A (2): 415-423 (2010)

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Other publications of authors with the same name

Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . ASP-DAC, page 103-104. IEEE, (2013)Single inductor dual output DC-DC converter design with exclusive control., , , , , , , , , and 6 other author(s). APCCAS, page 436-439. IEEE, (2012)DC-DC converter with continuous-time feed-forward Sigma-Delta modulator control., , , , , , , , , and 4 other author(s). APCCAS, page 65-68. IEEE, (2012)New architecture for envelope-tracking power amplifier for base station., , , , , , , and . APCCAS, page 296-299. IEEE, (2008)A New Procedure for Measuring High-Accuracy Probability Density Functions., , , , , , and . Asian Test Symposium, page 185-190. IEEE Computer Society, (2012)Post-Silicon Jitter Measurements., , , and . Asian Test Symposium, page 258-263. IEEE Computer Society, (2012)A clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . VLSIC, page 142-143. IEEE, (2012)Total Harmonic Distortion Measurement System of Electronic Devices up to 100 MHz With Remarkable Sensitivity., , , , and . IEEE Trans. Instrumentation and Measurement, 56 (6): 2360-2368 (2007)Two-Tone Signal Generation for ADC Testing., , , , , , , and . IEICE Transactions, 96-C (6): 850-858 (2013)A Study on Loop Gain Measurement Method Using Output Impedance in DC-DC Buck Converter., , and . IEICE Transactions, 101-B (9): 1940-1948 (2018)