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A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

K. Niitsu, N. Harigai, D. Hirabayashi, D. Oki, M. Sakurai, O. Kobayashi, T. Yamaguchi, and H. Kobayashi. VLSIC, page 142-143. IEEE, (2012)

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A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.K. Niitsu, N. Harigai, D. Hirabayashi, D. Oki, M. Sakurai, O. Kobayashi, T. Yamaguchi, and H. Kobayashi. VLSIC, page 142-143. IEEE, (2012)What Should Software Practitioners Know for Adopting Product Line Software Engineering?.O. Kobayashi. APSEC, page 565-566. IEEE Computer Society, (2004)Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.K. Niitsu, N. Harigai, D. Hirabayashi, D. Oki, M. Sakurai, O. Kobayashi, T. Yamaguchi, and H. Kobayashi. ASP-DAC, page 103-104. IEEE, (2013)Multi-bit Sigma-Delta TDC Architecture with Improved Linearity.S. Uemori, M. Ishii, H. Kobayashi, D. Hirabayashi, Y. Arakawa, Y. Doi, O. Kobayashi, T. Matsuura, K. Niitsu, Y. Yano and 3 other author(s). J. Electronic Testing, 29 (6): 879-892 (2013)Two-Tone Signal Generation for ADC Testing.K. Kato, F. Abe, K. Wakabayashi, C. Gao, T. Yamada, H. Kobayashi, O. Kobayashi, and K. Niitsu. IEICE Transactions, 96-C (6): 850-858 (2013)Two-Tone Signal Generation for Communication Application ADC Testing.K. Kato, F. Abe, K. Wakabayashi, C. Gao, T. Yamada, H. Kobayashi, O. Kobayashi, and K. Niitsu. Asian Test Symposium, page 179-184. IEEE Computer Society, (2012)Multi-bit sigma-delta TDC architecture with self-calibration.S. Uemori, M. Ishii, H. Kobayashi, Y. Doi, O. Kobayashi, T. Matsuura, K. Niitsu, Y. Arakawa, D. Hirabayashi, Y. Yano and 3 other author(s). APCCAS, page 671-674. IEEE, (2012)Simulation of the trajectory of a punted rugby ball taking into account the asymmetrical pressure distribution caused by the seams.K. Seo, O. Kobayashi, M. Murakami, D. Yorita, H. Nagai, and K. Asai. J. Visualization, 13 (2): 97-105 (2010)Linearity enhancement algorithms for I-Q signal generation - DWA and self-calibration techniques.M. Murakami, H. Kobayashi, S. Mohyar, T. Miki, and O. Kobayashi. ASICON, page 1-4. IEEE, (2015)Low-distortion signal generation for ADC testing.F. Abe, Y. Kobayashi, K. Sawada, K. Kato, O. Kobayashi, and H. Kobayashi. ITC, page 1-10. IEEE Computer Society, (2014)

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A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.

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A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.