Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

18-GHz Clock Distribution Using a Coupled VCO Array.

T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda. IEICE Transactions, 90-C (4): 811-822 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Yamaguchi, Hisakatsu

add a person with the name Yamaguchi, Hisakatsu

Other publications of authors with the same name

18-GHz Clock Distribution Using a Coupled VCO Array.T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda. IEICE Transactions, 90-C (4): 811-822 (2007)Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs.J. Liang, A. Sheikholeslami, H. Tamura, Y. Ogata, and H. Yamaguchi. J. Solid-State Circuits, 53 (9): 2696-2708 (2018)Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.H. Tamura, M. Kibune, H. Yamaguchi, K. Kanda, K. Gotoh, H. Ishida, and J. Ogawa. IEICE Transactions, 89-C (3): 300-313 (2006)A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS.O. Tyshchenko, A. Sheikholeslami, H. Tamura, Y. Tomita, H. Yamaguchi, M. Kibune, and T. Yamamoto. ISSCC, page 166-167. IEEE, (2010)A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution.T. Hashida, Y. Tomita, Y. Ogata, K. Suzuki, S. Suzuki, T. Nakao, Y. Terao, S. Honda, S. Sakabayashi, R. Nishiyama and 6 other author(s). VLSIC, page 1-2. IEEE, (2014)A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS.H. Miyaoka, F. Terasawa, M. Kudo, H. Kano, A. Matsuda, N. Shirai, S. Kawai, T. Shibasaki, T. Danjo, Y. Ogata and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)10-40 Gb/s I/O design for data communications.K. Chang, T. Carusone, A. Sheikholeslami, B. Payne, M. Moyal, J. Stonick, and H. Yamaguchi. ISSCC, page 502-503. IEEE, (2012)F3: Emerging technologies for wireline communication.E. Alon, A. Emami, G. den Besten, I. Fujimori, T. Kuroda, M. Nogawa, and H. Yamaguchi. ISSCC, page 504-505. IEEE, (2013)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS.T. Shibasaki, T. Danjo, Y. Ogata, Y. Sakai, H. Miyaoka, F. Terasawa, M. Kudo, H. Kano, A. Matsuda, S. Kawai and 7 other author(s). ISSCC, page 64-65. IEEE, (2016)20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range.T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda. J. Solid-State Circuits, 43 (3): 610-618 (2008)

PUMA

Disambiguation of "Yamaguchi, Hisakatsu"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

18-GHz Clock Distribution Using a Coupled VCO Array.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Yamaguchi, Hisakatsu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 18-GHz Clock Distribution Using a Coupled VCO Array.

Please choose a person to relate this publication to

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

18-GHz Clock Distribution Using a Coupled VCO Array.