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Disambiguation of "Yamamoto, Takuji"

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A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.

, , , , , , and . CICC, page 1-4. IEEE, (2010)

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Other publications of authors with the same name

A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link., , , , , and . J. Solid-State Circuits, 44 (8): 2085-2099 (2009)A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (12): 3258-3267 (2013)Trends and Challenges in Optical Communications Front-End., , and . ISSCC, page 394-395. IEEE, (2008)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)In-Line Measurement of Water Content in Ethanol Using a PVA-Coated Quartz Crystal Microbalance., , and . Sensors, 14 (1): 1564-1575 (2014)High-Speed Si-Bipolar IC Design for Multi-GB/s Optical Receivers., , , , , , and . IEEE Journal on Selected Areas in Communications, 9 (5): 645-651 (1991)High-speed transceivers: Standards, challenges, and future., , , , , and . ISSCC, page 522-523. IEEE, (2011)Transceiver circuits for optical communications., , , , , and . ISSCC, page 514-515. IEEE, (2010)A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology., , , , , , , , , and . J. Solid-State Circuits, 42 (1): 101-110 (2007)A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS., , , , , , , , , and 8 other author(s). J. Solid-State Circuits, 44 (12): 3580-3589 (2009)