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Disambiguation of "Kibune, Masaya"

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A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS.

, , , , and . ISSCC, page 154-156. IEEE, (2011)

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Other publications of authors with the same name

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS., , , , , , , , , and 13 other author(s). J. Solid-State Circuits, 45 (10): 2016-2029 (2010)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC., , , , , , , , , and 2 other author(s). IEICE Transactions, 93-C (3): 295-302 (2010)A Reference-Less Single-Loop Half-Rate Binary CDR., , , and . J. Solid-State Circuits, 50 (9): 2037-2047 (2015)A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS., , , and . ISSCC, page 436-438. IEEE, (2011)A pattern-guided adaptive equalizer in 65nm CMOS., , , , and . ISSCC, page 354-356. IEEE, (2011)A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS., , , , and . ISSCC, page 154-156. IEEE, (2011)A dynamic offset control technique for comparator design in scaled CMOS technology., , , , , , , and . CICC, page 495-498. IEEE, (2008)A 3x blind ADC-based CDR for a 20 dB loss channel., , , , , and . IEEE Trans. on Circuits and Systems, 62-I (6): 1658-1667 (2015)On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs., , , , and . VLSIC, page 1-2. IEEE, (2014)Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies., , , , , , and . IEICE Transactions, 89-C (3): 300-313 (2006)