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Disambiguation of "Tamura, Hirotaka"

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A pattern-guided adaptive equalizer in 65nm CMOS.

, , , , and . ISSCC, page 354-356. IEEE, (2011)

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Other publications of authors with the same name

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers., , , , and . CICC, page 413-416. IEEE, (2006)A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS., , , , , , , , , and 13 other author(s). J. Solid-State Circuits, 45 (10): 2016-2029 (2010)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC., , , , , , , , , and 2 other author(s). IEICE Transactions, 93-C (3): 295-302 (2010)A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX., , , , , , , , , and . J. Solid-State Circuits, 42 (12): 2726-2735 (2007)Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs., , , , and . J. Solid-State Circuits, 53 (9): 2696-2708 (2018)18-GHz Clock Distribution Using a Coupled VCO Array., , , , , and . IEICE Transactions, 90-C (4): 811-822 (2007)A pattern-guided adaptive equalizer in 65nm CMOS., , , , and . ISSCC, page 354-356. IEEE, (2011)A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS., , , , and . ISSCC, page 154-156. IEEE, (2011)A dynamic offset control technique for comparator design in scaled CMOS technology., , , , , , , and . CICC, page 495-498. IEEE, (2008)