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The Transmogrifier-2: a 1 million gate rapid-prototyping system., , , , and . IEEE Trans. VLSI Syst., 6 (2): 188-198 (1998)Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI., , , , and . IEEE Trans. on Circuits and Systems, 55-I (5): 1306-1315 (2008)A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers., , , , and . CICC, page 413-416. IEEE, (2006)An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling., , and . SoCC, page 297-300. IEEE, (2004)The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System., , , , and . FPGA, page 53-61. ACM, (1997)A Field Programmable Accelerator for Compiled-Code Applications., , and . ICCD, page 491-496. IEEE Computer Society, (1993)An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology., , , , , , , , , and 1 other author(s). ISSCC, page 352-354. IEEE, (2011)Performance of edge tap decision feedback equalization methods for wireline receivers., , , , , , and . NEWCAS, page 5-8. IEEE, (2014)Signaling capacity of FR4 PCB traces for chip-to-chip communication., , , and . ISCAS (5), page 85-88. IEEE, (2003)