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A Continuous-Time 0-3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS., , , , and . J. Solid-State Circuits, 49 (12): 2868-2877 (2014)A pattern-guided adaptive equalizer in 65nm CMOS., , , , and . ISSCC, page 354-356. IEEE, (2011)A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS., , , , and . ISSCC, page 154-156. IEEE, (2011)High-speed transceivers: Standards, challenges, and future., , , , , and . ISSCC, page 522-523. IEEE, (2011)Real-time sound localization using field-programmable gate arrays., , and . ICASSP (2), page 573-576. IEEE, (2003)A 3x blind ADC-based CDR for a 20 dB loss channel., , , , , and . IEEE Trans. on Circuits and Systems, 62-I (6): 1658-1667 (2015)On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs., , , , and . VLSIC, page 1-2. IEEE, (2014)Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI., , , , and . IEEE Trans. on Circuits and Systems, 55-I (5): 1306-1315 (2008)A Novel STT-MRAM Cell With Disturbance-Free Read Operation., and . IEEE Trans. on Circuits and Systems, 60-I (6): 1534-1547 (2013)An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset"., , , , and . IEEE Trans. on Circuits and Systems, 61-I (7): 2129-2138 (2014)