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A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS., , , , and . VLSI-DAT, page 1-4. IEEE, (2012)A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing., , , and . ISSCC, page 452-614. IEEE, (2007)A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration., , , and . ISSCC, page 384-385. IEEE, (2010)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC., , , , , , , , , and 2 other author(s). IEICE Transactions, 93-C (3): 295-302 (2010)Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances., , , , and . DAC, page 909-912. ACM, (2010)Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit., , , and . ASP-DAC, page 498-503. IEEE, (2009)Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality., , , and . IEICE Transactions, 92-A (12): 3035-3043 (2009)A 10-b 50-MS/s 820- μ W SAR ADC With On-Chip Digital Calibration., , , and . IEEE Trans. Biomed. Circuits and Systems, 4 (6): 410-416 (2010)A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS., , , , and . J. Solid-State Circuits, 49 (3): 673-682 (2014)Split capacitor DAC mismatch calibration in successive approximation ADC., , , , , , , , , and 2 other author(s). CICC, page 279-282. IEEE, (2009)