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Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.

Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and T. Kuroda. IEICE Transactions, 93-C (3): 295-302 (2010)

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Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.H. Tamura, M. Kibune, H. Yamaguchi, K. Kanda, K. Gotoh, H. Ishida, and J. Ogawa. IEICE Transactions, 89-C (3): 300-313 (2006)Split capacitor DAC mismatch calibration in successive approximation ADC.Y. Chen, X. Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada, M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa and 2 other author(s). CICC, page 279-282. IEEE, (2009)A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro.J. Ogawa, and M. Horowitz. Intelligent Memory Systems, volume 2107 of Lecture Notes in Computer Science, page 1-14. Springer, (2000)18-GHz Clock Distribution Using a Coupled VCO Array.T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda. IEICE Transactions, 90-C (4): 811-822 (2007)20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range.T. Shibasaki, H. Tamura, K. Kanda, H. Yamaguchi, J. Ogawa, and T. Kuroda. J. Solid-State Circuits, 43 (3): 610-618 (2008)A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX.N. Nedovic, N. Tzartzanis, H. Tamura, F. Rotella, M. Wiklund, Y. Mizutani, Y. Okaniwa, T. Kuroda, J. Ogawa, and W. Walker. ISSCC, page 224-598. IEEE, (2007)A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS.H. Yamaguchi, H. Tamura, Y. Doi, Y. Tomita, T. Hamada, M. Kibune, S. Ohmoto, K. Tateishi, O. Tyshchenko, A. Sheikholeslami and 5 other author(s). ISSCC, page 168-169. IEEE, (2010)A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process.Y. Doi, S. Masaki, T. Chiba, H. Higashi, H. Yamaguchi, H. Takauchi, H. Ishida, K. Gotoh, J. Ogawa, and H. Tamura. CICC, page 131-134. IEEE, (2005)A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS.O. Tyshchenko, A. Sheikholeslami, H. Tamura, M. Kibune, H. Yamaguchi, and J. Ogawa. J. Solid-State Circuits, 45 (6): 1091-1098 (2010)A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS.Y. Tomita, H. Tamura, M. Kibune, J. Ogawa, K. Gotoh, and T. Kuroda. J. Solid-State Circuits, 42 (3): 627-636 (2007)

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Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.

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Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC.