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A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS., , , , , , , , , and 13 other author(s). J. Solid-State Circuits, 45 (10): 2016-2029 (2010)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC., , , , , , , , , and 2 other author(s). IEICE Transactions, 93-C (3): 295-302 (2010)A dynamic offset control technique for comparator design in scaled CMOS technology., , , , , , , and . CICC, page 495-498. IEEE, (2008)A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 168-169. IEEE, (2010)A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology., , , , , , , and . IEICE Transactions, 93-A (12): 2456-2462 (2010)Using Symbolic Model Checking to Detect Service Interactions in Telecommunication Services., , , and . ICOIN (1), volume 2343 of Lecture Notes in Computer Science, page 641-651. Springer, (2002)Inferring win-lose product network from user behavior., , , , , and . WI, page 426-433. ACM, (2017)Split capacitor DAC mismatch calibration in successive approximation ADC., , , , , , , , , and 2 other author(s). CICC, page 279-282. IEEE, (2009)