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Disambiguation of "Shibuya, Toshiyuki"

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Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances.

, , , , and . DAC, page 909-912. ACM, (2010)

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Other publications of authors with the same name

Efficient Power Network Analysis Considering Multidomain Clock Gating., , , , , , , , , and 2 other author(s). IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (9): 1348-1358 (2009)A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel., , , , , , , , , and . ISSCC, page 346-348. IEEE, (2011)"Condition-based" dummy fill insertion method based on ECP and CMP predictive models., , , , , , , , and . ISQED, page 198-205. IEEE, (2010)Generation of yield-embedded Pareto-front for simultaneous optimization of yield and performances., , , , and . DAC, page 909-912. ACM, (2010)Large scale circuit partitioning with loose/stable net removal and signal flow based clustering., , , , and . ICCAD, page 441-446. IEEE Computer Society / ACM, (1997)A New Strategy for Simultaneous Escape Based on Boundary Routing., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (2): 205-214 (2011)Conference Reports: Recap of the 24th Asia and South Pacific Design Automation Conference.. IEEE Design & Test, 36 (4): 57-58 (2019)Fast power network analysis with multiple clock domains., , , , , , , , , and . ICCD, page 456-463. IEEE, (2007)A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS., , , , , , , , , and . ISSCC, page 28-29. IEEE, (2013)PDL: A New Physical Synthesis Methodology., , , , and . ISQED, page 348-354. IEEE Computer Society, (2003)