Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment., , and . DAC, page 414-419. (1995)Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis., , , , and . DATE, page 610-615. IEEE Computer Society, (2004)A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel., , , , , , , , , and . ISSCC, page 346-348. IEEE, (2011)Analyzing timing uncertainty in mesh-based clock architectures., , and . DATE, page 1097-1102. European Design and Automation Association, Leuven, Belgium, (2006)A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS., , , , , , , , , and 13 other author(s). J. Solid-State Circuits, 45 (10): 2016-2029 (2010)Accurate Substrate Noise Analysis Based on Library Module Characterization., and . VLSI Design, page 355-362. IEEE Computer Society, (2006)A sliding window scheme for accurate clock mesh analysis., , , , , , and . ICCAD, page 939-946. IEEE Computer Society, (2005)Clock Distribution Architectures: A Comparative Study., , , , , , , and . ISQED, page 85-91. IEEE Computer Society, (2006)