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Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis.

Y. Lin, S. Huang, K. Tsai, W. Cheng, S. Sunter, Y. Chou, and D. Kwai. IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (5): 737-747 (2013)

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Hanchuan Wu University of Stuttgart

Xiaoyu Cheng University of Stuttgart

Yongxiang Wu University of Stuttgart

Tiffany Cheng University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Other publications of authors with the same name

Logic BIST Using Constrained Scan Cells.L. Lai, T. Rinderknecht, W. Cheng, and J. Patel. VTS, page 199-205. IEEE Computer Society, (2004)Automatic Test Pattern Generation for Interconnect Open Defects.S. Spinner, I. Polian, P. Engelke, B. Becker, M. Keim, and W. Cheng. VTS, page 181-186. IEEE Computer Society, (2008)Identify problematic layout patterns through volume diagnosis.W. Cheng. VLSI-DAT, page 1. IEEE, (2015)At-Speed Scan Test Method for the Timing Optimization and Calibration.K. Tsai, R. Guo, and W. Cheng. Asian Test Symposium, page 430-433. IEEE Computer Society, (2009)Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults.Y. Huang, W. Cheng, C. Hsieh, H. Tseng, A. Huang, and Y. Hung. Asian Test Symposium, page 44-49. IEEE Computer Society, (2003)Testing Delay Faults in Embedded CAMs.X. Du, S. Reddy, J. Rayhawk, and W. Cheng. Asian Test Symposium, page 378-383. IEEE Computer Society, (2003)Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.Y. Huang, W. Cheng, C. Tsai, N. Mukherjee, O. Samman, Y. Zaidan, and S. Reddy. Asian Test Symposium, page 265-. IEEE Computer Society, (2001)A Hybrid Flow for Memory Failure Bitmap Classification.J. Li, Y. Huang, W. Cheng, C. Schuermyer, D. Xiang, E. Faehn, and R. Farrugia. Asian Test Symposium, page 314-319. IEEE Computer Society, (2012)Core - Clustering Based SOC Test Scheduling Optimization.Y. Huang, S. Reddy, and W. Cheng. Asian Test Symposium, page 405-410. IEEE Computer Society, (2002)Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng.W. Cheng. Asian Test Symposium, page 10-. IEEE Computer Society, (2000)