Author of the publication

Automatic Test Pattern Generation for Interconnect Open Defects.

, , , , , and . VTS, page 181-186. IEEE Computer Society, (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement., and . VLSI Design, page 21-23. IEEE Computer Society, (2015)Pulse-Vanishing Test for Interposers Wires in 2.5-D IC., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (8): 1258-1268 (2014)Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (5): 737-747 (2013)On Concurrent Test of Core-Based SOC Design., , , , , , and . J. Electronic Testing, 18 (4-5): 401-414 (2002)Oscillation-Based Prebond TSV Test., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (9): 1440-1444 (2013)Automatic Test Pattern Generation for Interconnect Open Defects., , , , , and . VTS, page 181-186. IEEE Computer Society, (2008)Logic BIST Using Constrained Scan Cells., , , and . VTS, page 199-205. IEEE Computer Society, (2004)Identify problematic layout patterns through volume diagnosis.. VLSI-DAT, page 1. IEEE, (2015)At-Speed Scan Test Method for the Timing Optimization and Calibration., , and . Asian Test Symposium, page 430-433. IEEE Computer Society, (2009)Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults., , , , , and . Asian Test Symposium, page 44-49. IEEE Computer Society, (2003)