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Diagnosis and Layout Aware (DLA) Scan Chain Stitching., , , , , , , , , and 5 other author(s). IEEE Trans. VLSI Syst., 23 (3): 466-479 (2015)STDF Memory Fail Datalog Standard., , , , , , , , , and . VTS, page 209-214. IEEE Computer Society, (2009)Logic BIST with Scan Chain Segmentation., , , and . ITC, page 57-66. IEEE Computer Society, (2004)Detection and Diagnosis of Static Scan Cell Internal Defect., , , and . ITC, page 1-10. IEEE Computer Society, (2008)Signature Based Diagnosis for Logic BIST., , , , and . ITC, page 1-9. IEEE Computer Society, (2006)Logic BIST Using Constrained Scan Cells., , , and . VTS, page 199-205. IEEE Computer Society, (2004)Hardware Ef.cient LBISTWith Complementary Weights., , , and . ICCD, page 479-484. IEEE Computer Society, (2005)X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis., , , , , , , and . IEEE Design & Test of Computers, 24 (5): 476-485 (2007)Diagnosis and Layout Aware (DLA) scan chain stitching., , , , , , , , , and 5 other author(s). ITC, page 1-10. IEEE Computer Society, (2013)