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Enabling yield analysis with X-compact., , , and . ITC, page 9. IEEE Computer Society, (2005)Speed-Path Debug Using At-Speed Scan Test Patterns., , and . European Test Symposium, page 11-16. IEEE Computer Society, (2009)Diagnosis of Multiple Physical Defects Using Logic Fault Models., , , and . Asian Test Symposium, page 94-99. IEEE Computer Society, (2010)A Robust Automated Scan Pattern Mismatch Debugger., , and . ATS, page 309-314. IEEE Computer Society, (2008)Enhancing Transition Fault Model for Delay Defect Diagnosis., , , , , , , , and . ATS, page 179-184. IEEE Computer Society, (2008)Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive., , , , , and . VTS, page 66-71. IEEE Computer Society, (2006)Using Scan-Dump Values to Improve Functional-Diagnosis Methodology., , , , , and . VTS, page 231-238. IEEE Computer Society, (2007)Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns., , , , , and . Asian Test Symposium, page 35-40. IEEE Computer Society, (2009)Static test compaction for synchronous sequential circuits based on vector restoration., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 18 (7): 1040-1049 (1999)Material Removal Simulation of Multi-axis NC Milling Based on Spatial Partitioning Level of Detail Model., , , , and . CIT, page 536-540. IEEE Computer Society, (2012)