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Disambiguation of "Cheng, Wu-Tung"

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Identify problematic layout patterns through volume diagnosis.

. VLSI-DAT, page 1. IEEE, (2015)

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Hanchuan Wu University of Stuttgart

Xiaoyu Cheng University of Stuttgart

Yongxiang Wu University of Stuttgart

Tiffany Cheng University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

 

Other publications of authors with the same name

Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement., and . VLSI Design, page 21-23. IEEE Computer Society, (2015)Oscillation-Based Prebond TSV Test., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (9): 1440-1444 (2013)On Concurrent Test of Core-Based SOC Design., , , , , , and . J. Electronic Testing, 18 (4-5): 401-414 (2002)Pulse-Vanishing Test for Interposers Wires in 2.5-D IC., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (8): 1258-1268 (2014)Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (5): 737-747 (2013)Identify problematic layout patterns through volume diagnosis.. VLSI-DAT, page 1. IEEE, (2015)Automatic Test Pattern Generation for Interconnect Open Defects., , , , , and . VTS, page 181-186. IEEE Computer Society, (2008)Logic BIST Using Constrained Scan Cells., , , and . VTS, page 199-205. IEEE Computer Society, (2004)Scan based speed-path debug for a microprocessor., , , , , , and . European Test Symposium, page 207-212. IEEE Computer Society, (2010)Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault., , , , and . ITC, page 319-328. IEEE Computer Society, (2003)