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Disambiguation of "Huang, Shi-Yu"

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Pulse-Vanishing Test for Interposers Wires in 2.5-D IC.

, , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (8): 1258-1268 (2014)

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Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

Wei Yu University of Stuttgart

Zhenxiang Huang University of Stuttgart

Jingjing Huang University of Stuttgart

Abhishekkumar Shingala University of Stuttgart

 

Other publications of authors with the same name

A Fading Algorithm For Sequential Fault Diagnosis.. DFT, page 139-147. IEEE Computer Society, (2004)Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism., , , , and . IEEE Trans. on Circuits and Systems, 60-I (4): 908-917 (2013)AQUILA: An Equivalence Checking System for Large Sequential Designs., , , , and . IEEE Trans. Computers, 49 (5): 443-464 (2000)On Verifying the Correctness of Retimed Circuits., , and . Great Lakes Symposium on VLSI, page 277-. IEEE Computer Society, (1996)Decomposition of Extended Finite State Machine for Low Power Design., , and . DATE, page 11152-11153. IEEE Computer Society, (2003)Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation.. VTS, page 193-200. IEEE Computer Society, (2002)High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction., , , and . IEEE Trans. Circuits Syst. Video Techn., 22 (3): 340-351 (2012)Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (12): 2039-2048 (2015)General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (11): 1836-1846 (2015)A unified method for parametric fault characterization of post-bond TSVs., , , , and . ITC, page 1-10. IEEE Computer Society, (2012)