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Disambiguation of "Huang, Shi-Yu"

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Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects.

, , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (12): 2039-2048 (2015)

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Dr. rer. nat. Shiang-Yu Huang University of Stuttgart

Wei Yu University of Stuttgart

Zhenxiang Huang University of Stuttgart

Jingjing Huang University of Stuttgart

Abhishekkumar Shingala University of Stuttgart

 

Other publications of authors with the same name

A Fading Algorithm For Sequential Fault Diagnosis.. DFT, page 139-147. IEEE Computer Society, (2004)On Verifying the Correctness of Retimed Circuits., , and . Great Lakes Symposium on VLSI, page 277-. IEEE Computer Society, (1996)Decomposition of Extended Finite State Machine for Low Power Design., , and . DATE, page 11152-11153. IEEE Computer Society, (2003)Speeding Up The Byzantine Fault Diagnosis Using Symbolic Simulation.. VTS, page 193-200. IEEE Computer Society, (2002)A Light-and-Fast SLAM Algorithm for Robots in Indoor Environments Using Line Segment Map., , , and . J. Robotics, (2011)A novel methodology for transistor-level power estimation., , , and . ISLPED, page 67-72. IEEE, (1996)A fully cell-based design for timing measurement of memory., , , and . ITC, page 1-10. IEEE Computer Society, (2011)High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction., , , and . IEEE Trans. Circuits Syst. Video Techn., 22 (3): 340-351 (2012)Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (12): 2039-2048 (2015)General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (11): 1836-1846 (2015)