Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis.

Y. Lin, S. Huang, K. Tsai, W. Cheng, S. Sunter, Y. Chou, and D. Kwai. IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (5): 737-747 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Michel Choudalakis University of Stuttgart

Roland Falk University of Stuttgart

Daniel Fahse University of Stuttgart

Jan Falter University of Stuttgart

Rouven Fauser University of Stuttgart

Other publications of authors with the same name

3D-IC BISR for stacked memories using cross-die spares.C. Chi, Y. Chou, D. Kwai, Y. Hsiao, C. Wu, Y. Hsing, L. Denq, and T. Lin. VLSI-DAT, page 1-4. IEEE, (2012)A hybrid built-in self-test scheme for DRAMs.C. Yang, J. Li, Y. Yu, K. Wu, C. Lo, C. Chen, J. Lai, D. Kwai, and Y. Chou. VLSI-DAT, page 1-4. IEEE, (2015)A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.Y. You, C. Hou, L. Chang, J. Li, C. Lo, D. Kwai, Y. Chou, and C. Wu. VTS, page 1-6. IEEE Computer Society, (2013)Hierarchical Test Integration Methodology for 3-D ICs.C. Chou, J. Li, Y. Yu, C. Lo, D. Kwai, and Y. Chou. IEEE Design & Test, 32 (4): 59-70 (2015)General Modular Multiplication by Block Multiplication and Table Lookup.C. Wu, and Y. Chou. ISCAS, page 295-298. IEEE, (1994)A self-testing and calibration method for embedded successive approximation register ADC.X. Huang, P. Kang, H. Chang, J. Huang, Y. Chou, Y. Lee, D. Kwai, and C. Wu. ASP-DAC, page 713-718. IEEE, (2011)CAD reference flow for 3D via-last integrated circuits.C. Lin, D. Kwai, Y. Chou, T. Chen, and W. Wu. ASP-DAC, page 187-192. IEEE, (2010)A built-in self-repair scheme for DRAMs with spare rows, columns, and bits.C. Hou, Y. Chen, J. Li, C. Lo, D. Kwai, and Y. Chou. ITC, page 1-7. IEEE, (2016)On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC.S. Fang, C. Lin, W. Liao, C. Huang, L. Chen, H. Chen, I. Lee, D. Kwai, and Y. Chou. ISVLSI, page 459-464. IEEE Computer Society, (2017)SRAM delay fault modeling and test algorithm development.R. Huang, Y. Lai, Y. Chou, and C. Wu. ASP-DAC, page 104-109. IEEE Computer Society, (2004)