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Economic Analysis of the HOY Wireless Test Methodology., , , and . IEEE Design & Test of Computers, 27 (3): 20-30 (2010)A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories., , , , and . MTDT, page 65-69. IEEE Computer Society, (2004)A prototype of a wireless-based test system., , , , , , , , , and 2 other author(s). SoCC, page 225-228. IEEE, (2007)3D-IC BISR for stacked memories using cross-die spares., , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)SOC Test Architecture and Method for 3-D ICs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (10): 1645-1649 (2010)An SOC Test Integration Platform and Its Industrial Realization., , , , , , , and . ITC, page 1213-1222. IEEE Computer Society, (2004)Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques., , , , , and . ATS, page 245-250. IEEE Computer Society, (2008)A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing., , , , , , , , , and 9 other author(s). DAC, page 771-776. ACM, (2011)A Memory Built-In Self-Repair Scheme Based on Configurable Spares., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (6): 919-929 (2011)A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories., , , and . MTDT, page 53-. IEEE Computer Society, (2003)