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Disambiguation of "Chi, Chun-Chuan"

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3D-IC BISR for stacked memories using cross-die spares.

, , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)

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Haripriya Chinnaraj University of Stuttgart

Simone Chiocchetti University of Stuttgart

Maria Chira University of Stuttgart

Phi-Long Chung University of Stuttgart

 

Other publications of authors with the same name

3D DfT architecture for pre-bond and post-bond testing., , , and . 3DIC, page 1-8. IEEE, (2010)Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base., , , and . ITC, page 1-10. IEEE Computer Society, (2011)A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper., , , and . J. Electronic Testing, 28 (1): 73-92 (2012)3D-IC BISR for stacked memories using cross-die spares., , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)Test Integration for SOC Supporting Very Low-Cost Testers., , , and . Asian Test Symposium, page 287-292. IEEE Computer Society, (2009)DfT Architecture for 3D-SICs with Multiple Towers., , , and . European Test Symposium, page 51-56. IEEE Computer Society, (2011)3D-IC interconnect test, diagnosis, and repair., , , and . VTS, page 1-6. IEEE Computer Society, (2013)Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base., , , and . Asian Test Symposium, page 451-456. IEEE Computer Society, (2011)On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs., , , , , and . IEEE Design & Test, 31 (4): 16-26 (2014)A low-cost and scalable test architecture for multi-core chips., , and . European Test Symposium, page 30-35. IEEE Computer Society, (2010)