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A Hybrid Flow for Memory Failure Bitmap Classification.

J. Li, Y. Huang, W. Cheng, C. Schuermyer, D. Xiang, E. Faehn, and R. Farrugia. Asian Test Symposium, page 314-319. IEEE Computer Society, (2012)

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Jingcheng Wu University of Stuttgart

Hanchuan Wu University of Stuttgart

Xiaoyu Cheng University of Stuttgart

Yongxiang Wu University of Stuttgart

Tiffany Cheng University of Stuttgart

Other publications of authors with the same name

Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement.W. Cheng, and S. Reddy. VLSI Design, page 21-23. IEEE Computer Society, (2015)Automatic Test Pattern Generation for Interconnect Open Defects.S. Spinner, I. Polian, P. Engelke, B. Becker, M. Keim, and W. Cheng. VTS, page 181-186. IEEE Computer Society, (2008)Logic BIST Using Constrained Scan Cells.L. Lai, T. Rinderknecht, W. Cheng, and J. Patel. VTS, page 199-205. IEEE Computer Society, (2004)Identify problematic layout patterns through volume diagnosis.W. Cheng. VLSI-DAT, page 1. IEEE, (2015)Hardware Ef.cient LBISTWith Complementary Weights.L. Lai, J. Patel, T. Rinderknecht, and W. Cheng. ICCD, page 479-484. IEEE Computer Society, (2005)Compactor Independent Direct Diagnosis.W. Cheng, K. Tsai, Y. Huang, N. Tamarapalli, and J. Rajski. Asian Test Symposium, page 204-209. IEEE Computer Society, (2004)At-Speed Scan Test Method for the Timing Optimization and Calibration.K. Tsai, R. Guo, and W. Cheng. Asian Test Symposium, page 430-433. IEEE Computer Society, (2009)Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults.Y. Huang, W. Cheng, C. Hsieh, H. Tseng, A. Huang, and Y. Hung. Asian Test Symposium, page 44-49. IEEE Computer Society, (2003)Testing Delay Faults in Embedded CAMs.X. Du, S. Reddy, J. Rayhawk, and W. Cheng. Asian Test Symposium, page 378-383. IEEE Computer Society, (2003)Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.Y. Huang, W. Cheng, C. Tsai, N. Mukherjee, O. Samman, Y. Zaidan, and S. Reddy. Asian Test Symposium, page 265-. IEEE Computer Society, (2001)