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A Hybrid Flow for Memory Failure Bitmap Classification.

, , , , , , and . Asian Test Symposium, page 314-319. IEEE Computer Society, (2012)

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Partial Scan Design Based on Circuit State Information and Functional Analysis., and . IEEE Trans. Computers, 53 (3): 276-287 (2004)Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST., , and . IEEE Trans. Computers, 56 (12): 1619-1628 (2007)Scan BIST with biased scan test signals., , and . Science in China Series F: Information Sciences, 51 (7): 881-895 (2008)Fault-Tolerant Routing in Hypercube Multicomputers Using Local Safety Information.. IEEE Trans. Parallel Distrib. Syst., 12 (9): 942-951 (2001)Balancing virtual channel utilization for deadlock-free routing in torus networks., , and . The Journal of Supercomputing, 71 (8): 3094-3115 (2015)Fault-tolerant routing in hypercubes using partial path set-up.. Future Generation Comp. Syst., 22 (7): 812-819 (2006)Thermal-aware test scheduling for NOC-based 3D integrated circuits., , , and . VLSI-SoC, page 96-101. IEEE, (2013)New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets., , and . VLSI Design, page 221-226. IEEE Computer Society, (2009)A Unified Solution to Scan Test Volume, Time, and Power Minimization., , , and . VLSI Design, page 9-14. IEEE Computer Society, (2010)A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (6): 999-1012 (2008)