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Core - Clustering Based SOC Test Scheduling Optimization.

, , and . Asian Test Symposium, page 405-410. IEEE Computer Society, (2002)

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Reducing Scan Shift Power at RTL., , , , and . VTS, page 139-146. IEEE Computer Society, (2008)Memory BIST Using ESP., , , , and . VTS, page 243-248. IEEE Computer Society, (2004)On Improving Diagnostic Test Generation for Scan Chain Failures., , , , and . Asian Test Symposium, page 41-46. IEEE Computer Society, (2009)On Using Design Partitioning to Reduce Diagnosis Memory Footprint., , , , and . Asian Test Symposium, page 219-225. IEEE Computer Society, (2011)Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 32 (8): 1265-1273 (2013)Improve speed path identification with suspect path expressions., , , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Diagnosing timing related cell internal defects for FinFET technology., , , , and . VLSI-DAT, page 1-4. IEEE, (2015)A complete test set to diagnose scan chain failures., , and . ITC, page 1-10. IEEE Computer Society, (2007)Interconnect open defect diagnosis with minimal physical information., , , , , and . ITC, page 1-10. IEEE Computer Society, (2007)Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis., , , , , , , , , and 1 other author(s). ITC, page 1-9. IEEE Computer Society, (2006)