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Disambiguation of "Barth, John"

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An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.

, , , , , , , , , , , , and . ESSCIRC, page 66-69. IEEE, (2008)

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Dr. rer. nat. Simon Barth University of Stuttgart

John Nixon University of Stuttgart

Rahul Barthwal University of Stuttgart

Isaac Henderson Johnson Jeyakumar University of Stuttgart

Lukas Bartholomäus University of Stuttgart

 

Other publications of authors with the same name

Embedded DRAM built in self test and methodology for test insertion., , , , , , , and . ITC, page 975-984. IEEE Computer Society, (2001)A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier., , , , , , , , , and 7 other author(s). ISSCC, page 486-617. IEEE, (2007)A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 86-95 (2008)A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 44 (4): 1216-1226 (2009)A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 64-75 (2011)Isolated Preset Architecture for a 32nm SOI embedded DRAM macro., , , , , , and . VLSIC, page 110-111. IEEE, (2012)A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache., , , , , , , , , and . ISSCC, page 342-343. IEEE, (2010)Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond., , , , , , , , , and 8 other author(s). ICICDT, page 1-4. IEEE, (2012)An on-chip dual supply charge pump system for 45nm PD SOI eDRAM., , , , , , , , , and 3 other author(s). ESSCIRC, page 66-69. IEEE, (2008)Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering., , , , , , , , and . IBM J. Res. Dev., 46 (6): 675-690 (2002)