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Disambiguation of "Kirihata, Toshiaki"

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An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.

, , , , , , , , , , , , and . ESSCIRC, page 66-69. IEEE, (2008)

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Other publications of authors with the same name

A low-noise TTL-compatible CMOS off-chip driver circuit., , , and . IBM Journal of Research and Development, 39 (1-2): 105-112 (1995)Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM., , , , , , and . J. Solid-State Circuits, 48 (4): 940-947 (2013)An on-chip dual supply charge pump system for 45nm PD SOI eDRAM., , , , , , , , , and 3 other author(s). ESSCIRC, page 66-69. IEEE, (2008)Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip., , , , , , , , , and 1 other author(s). ICCD, page 279-285. IEEE Computer Society, (1997)Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications., , , , , , , , , and 3 other author(s). IRPS, page 2. IEEE, (2015)A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 51 (1): 230-239 (2016)A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 406-407. IEEE, (2008)Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM., , , , , and . VLSIC, page 146-147. IEEE, (2012)A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 64-75 (2011)A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM., , , , , and . J. Solid-State Circuits, 48 (11): 2934-2943 (2013)