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Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current., , , , , , , , , and . IEICE Transactions, 95-C (6): 1089-1097 (2012)A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments., , , , and . IEICE Transactions, 95-A (1): 263-266 (2012)Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function., , , and . ReConFig, page 223-228. IEEE Computer Society, (2011)A Compact Rijndael Hardware Architecture with S-Box Optimization., , , and . ASIACRYPT, volume 2248 of Lecture Notes in Computer Science, page 239-254. Springer, (2001)Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI., and . ISC, volume 2433 of Lecture Notes in Computer Science, page 48-62. Springer, (2002)High-Performance Concurrent Error Detection Scheme for AES Hardware., , , and . CHES, volume 5154 of Lecture Notes in Computer Science, page 100-112. Springer, (2008)High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching., , , , and . CHES, volume 4249 of Lecture Notes in Computer Science, page 187-200. Springer, (2006)Prototyping Platform for Performance Evaluation of SHA-3 Candidates., , , , , , , , , and 3 other author(s). HOST, page 60-63. IEEE Computer Society, (2010)Profiling attack using multivariate regression analysis., , , and . IEICE Electronic Express, 7 (15): 1139-1144 (2010)Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers., , , and . IEEE Trans. VLSI Syst., 19 (7): 1136-1146 (2011)