PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Homma, Naofumi"

Author of the publication

copydeleteadd this publication to your clipboard
Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current.

, , , , , , , , , and . IEICE Transactions, 95-C (6): 1089-1097 (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Homma, Naofumi
add a person with the name Homma, Naofumi
 

Other publications of authors with the same name

Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language., , , , and . Multiple-Valued Logic and Soft Computing, 15 (4): 329-340 (2009)A Formal Approach to Designing Multiple-Valued Arithmetic Circuits., , and . Multiple-Valued Logic and Soft Computing, 24 (1-4): 21-34 (2015)Toward Formal Design of Practical Cryptographic Hardware Based on Galois Field Arithmetic., , and . IEEE Trans. Computers, 63 (10): 2604-2613 (2014)An on-chip glitchy-clock generator for testing fault injection attacks., , , , and . J. Cryptographic Engineering, 1 (4): 265-270 (2011)Graph-based evolutionary design of arithmetic circuits., , , , and . IEEE Trans. Evolutionary Computation, 6 (1): 86-100 (2002)Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques., , , , , and . DATE, page 1004-1009. IEEE, (2011)A Formal Approach to Designing Cryptographic Processors Based on $GF(2^m)$ Arithmetic Circuits., , and . IEEE Trans. Information Forensics and Security, 7 (1): 3-13 (2012)Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams., , , and . ISMVL, page 31. IEEE Computer Society, (2007)Design of Tamper-Resistant Registers for Multiple-Valued Cryptographic Processors., , , and . ISMVL, page 67-72. IEEE Computer Society, (2010)Chosen-message SPA attacks against FPGA-based RSA hardware implementations., , , and . FPL, page 35-40. IEEE, (2008)