%0 Journal Article %1 journals/jssc/BarthPNHFSMKRNC11 %A Barth, John %A Plass, Don %A Nelson, Erik %A Hwang, Charlie %A Fredeman, Gregory %A Sperling, Michael A. %A Mathews, Abraham %A Kirihata, Toshiaki %A Reohr, William R. %A Nair, Kavita %A Caon, Nianzheng %D 2011 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 64-75 %T A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache. %U http://dblp.uni-trier.de/db/journals/jssc/jssc46.html#BarthPNHFSMKRNC11 %V 46

@article{journals/jssc/BarthPNHFSMKRNC11, added-at = {2022-02-25T00:00:00.000+0100}, author = {Barth, John and Plass, Don and Nelson, Erik and Hwang, Charlie and Fredeman, Gregory and Sperling, Michael A. and Mathews, Abraham and Kirihata, Toshiaki and Reohr, William R. and Nair, Kavita and Caon, Nianzheng}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2727fe6e0670f7128508ffa8c60cfe9c5/dblp}, ee = {https://doi.org/10.1109/JSSC.2010.2084470}, interhash = {f3455fc42b3285d9e0eea73f2cd3917d}, intrahash = {727fe6e0670f7128508ffa8c60cfe9c5}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {64-75}, timestamp = {2022-03-01T06:21:56.000+0100}, title = {A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc46.html#BarthPNHFSMKRNC11}, volume = 46, year = 2011 }