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SRAM device and cell co-design considerations in a 14nm SOI FinFET technology., , , , , , , and . ISCAS, page 2339-2342. IEEE, (2013)Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor., , , , , , , , , and 7 other author(s). CICC, page 235-238. IEEE, (2005)A 32nm 0.5V-supply dual-read 6T SRAM., , , , , , , , , and 5 other author(s). CICC, page 1-4. IEEE, (2010)The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM., , , , , , , and . IEEE Trans. on Circuits and Systems, 58-I (9): 2010-2016 (2011)TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip., , , , , , , , , and 8 other author(s). IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (10): 1537-1557 (2015)Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs., , , , , , , and . ISQED, page 33-40. IEEE Computer Society, (2007)Statistical yield analysis of silicon-on-insulator embedded DRAM., , , , , , , and . ISQED, page 190-194. IEEE Computer Society, (2009)SRAM Local Bit Line Access Failure Analyses., , , , , and . ISQED, page 204-209. IEEE Computer Society, (2006)Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology., , , , , and . IEEE Design & Test, 30 (6): 18-28 (2013)Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability., , , , , , and . ESSDERC, page 234-237. IEEE, (2013)