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The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.

, , , , , , , and . IEEE Trans. on Circuits and Systems, 58-I (9): 2010-2016 (2011)

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Guest Editors' Introduction: On-Chip Power Distribution Networks., and . IEEE Design & Test of Computers, 20 (3): 5-6 (2003)Simultaneous Layout Migration and Decomposition for Double Patterning Technology., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (2): 284-294 (2011)Hierarchical Multialgorithm Parallel Circuit Simulation., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (1): 45-58 (2011)A Methodology for Worst-Case Analysis of Integrated Circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 5 (1): 104-113 (1986)Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues., , , and . ASP-DAC, page 7-16. IEEE, (2012)2011 TAU power grid simulation contest: Benchmark suite and results., , , and . ICCAD, page 478-481. IEEE Computer Society, (2011)A framework for double patterning-enabled design., , , , , and . ICCAD, page 14-20. IEEE Computer Society, (2011)A Linear-Centric Simulation Framework for Parametric Fluctuations., , and . DATE, page 568-575. IEEE Computer Society, (2002)A Design Model for Random Process Variability., , , , and . ISQED, page 734-737. IEEE Computer Society, (2008)SRAM Local Bit Line Access Failure Analyses., , , , , and . ISQED, page 204-209. IEEE Computer Society, (2006)