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The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.

, , , , , , , and . IEEE Trans. on Circuits and Systems, 58-I (9): 2010-2016 (2011)

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A 32nm 0.5V-supply dual-read 6T SRAM., , , , , , , , , and 5 other author(s). CICC, page 1-4. IEEE, (2010)IBM POWER8 circuit design and energy optimization., , , , , , , , , and 13 other author(s). IBM Journal of Research and Development, (2015)The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM., , , , , , , and . IEEE Trans. on Circuits and Systems, 58-I (9): 2010-2016 (2011)POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor., , , , , , , , , and 14 other author(s). J. Solid-State Circuits, 46 (1): 145-161 (2011)Custom circuit design as a driver of microprocessor performance., , , , , , and . IBM Journal of Research and Development, 44 (6): 799-822 (2000)A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor., , , , , , , , , and 3 other author(s). ISSCC, page 344-345. IEEE, (2010)POWER7TM local clocking and clocked storage elements., , , , , , , and . ISSCC, page 178-179. IEEE, (2010)4.1 22nm Next-generation IBM System z microprocessor., , , , , , , , , and 21 other author(s). ISSCC, page 1-3. IEEE, (2015)Cell Broadband Engine processor: Design and implementation., , and . IBM Journal of Research and Development, 51 (5): 545-558 (2007)Cell Processor Low-Power Design Methodology., , , , , , , and . IEEE Micro, 25 (6): 71-78 (2005)