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On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation., , and . J. Solid-State Circuits, 42 (7): 1593-1606 (2007)A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 53 (4): 1214-1226 (2018)A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration., , , , , , , , , and . J. Solid-State Circuits, 51 (8): 1744-1755 (2016)A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS., , , , , , and . J. Solid-State Circuits, 55 (1): 19-26 (2020)Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS., , , , and . J. Solid-State Circuits, 55 (3): 731-743 (2020)Root cause identification of an hard-to-find on-chip power supply coupling fail., , , , , , and . ITC, page 1-7. IEEE Computer Society, (2012)The POWER8TM processor: Designed for big data, analytics, and cloud environments., , , , , , , , , and 10 other author(s). ICICDT, page 1-4. IEEE, (2014)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications., , , , , , and . ISSCC, page 94-95. IEEE, (2009)Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"., , , , , , and . J. Solid-State Circuits, 55 (4): 1124 (2020)Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 47 (4): 863-874 (2012)