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Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues.

, , , and . ASP-DAC, page 7-16. IEEE, (2012)

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High performance lithographic hotspot detection using hierarchically refined machine learning., , , and . ASP-DAC, page 775-780. IEEE, (2011)MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks., and . ASP-DAC, page 250-257. IEEE, (2008)A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography., , , , and . ASP-DAC, page 637-644. IEEE, (2010)Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (5): 820-831 (2016)TRIAD: a triple patterning lithography aware detailed router., , , and . CoRR, (2014)PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control., , , , and . CoRR, (2017)Electromigration-aware routing for 3D ICs with stress-aware EM modeling., , and . ICCAD, page 325-332. ACM, (2012)Wire density driven global routing for CMP variation and timing., , , and . ICCAD, page 487-492. ACM, (2006)A novel unified dummy fill insertion framework with SQP-based optimization method., , , , , and . ICCAD, page 88. ACM, (2016)Keep it straight: teaching placement how to better handle designs with datapaths., , , , , , and . ISPD, page 79-86. ACM, (2012)