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An advanced statistical compact model strategy for SRAM simulation at reduced VDD., , , , and . ESSDERC, page 205-208. IEEE, (2012)SRAM device and cell co-design considerations in a 14nm SOI FinFET technology., , , , , , , and . ISCAS, page 2339-2342. IEEE, (2013)Circuit design perspectives for Ge FinFET at 10nm and beyond., , , , , , , , , und 2 andere Autor(en). ISQED, Seite 57-60. IEEE, (2015)Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models., , , , , und . ICICDT, Seite 29-32. IEEE, (2013)Progress on carbon nanotube BEOL interconnects., , , , , , , , , und 11 andere Autor(en). DATE, Seite 937-942. IEEE, (2018)Secure, Performance-Oriented Data Management for nanoCMOS Electronics., , , , , , , , , und 1 andere Autor(en). eScience, Seite 87-94. IEEE Computer Society, (2008)Integrating Security Solutions to Support nanoCMOS Electronics Research., , , , , , , , , und 3 andere Autor(en). ISPA, Seite 71-79. IEEE Computer Society, (2008)Capturing intrinsic parameter fluctuations using the PSP compact model., , , , , , , und . DATE, Seite 650-653. IEEE, (2010)Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis., , , , , , , , , und . DATE, Seite 1537-1540. IEEE, (2011)Modeling and simulation of transistor and circuit variability and reliability., , , , , , , , und . CICC, Seite 1-8. IEEE, (2010)