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Disambiguation of "Nassif, Sani R."

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Statistical yield analysis of silicon-on-insulator embedded DRAM.

, , , , , , , and . ISQED, page 190-194. IEEE Computer Society, (2009)

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R. Koerner

R. Watty

Ph. D. Curtis Runstedler University of Stuttgart

Alchemy and Exemplary Poetry in Middle English Literature. The New Middle Ages Palgrave Macmillan, Cham, (2023)

Dr. -Ing. Kim Riedmüller University of Stuttgart

Materialgerechtes Fügen von Faserverbundprofilen, , , , and . Forschungsbericht, Universität Stuttgart, Institut für Leichtbau Entwerfen und Konstruieren, Stuttgart, (2014)

Jun. -Prof. Dr. -Ing. Alina Roitberg University of Stuttgart

On Transferability of Driver Observation Models from Simulated to Real Environments in Autonomous Cars, , , , and . 2023 IEEE 26th International Conference on Intelligent Transportation Systems (ITSC), page 3129-3134. IEEE, (2023)
On Transferability of Driver Observation Models from Simulated to Real Environments in Autonomous Cars, , , , and . 2023 IEEE 26th International Conference on Intelligent Transportation Systems (ITSC), page 3129-3134. IEEE, (2023)Quantized Distillation : Optimizing Driver Activity Recognition Models for Resource-Constrained Environments, , , , and . 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), page 5479-5486. IEEE, (2023)
 

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Testing and debugging delay faults in dynamic circuits., , , and . ITC, page 10. IEEE Computer Society, (2005)Benefits and Costs of Power-Gating Technique., , and . ICCD, page 559-566. IEEE Computer Society, (2005)Impact of Design-Manufacturing Interface on SoC Design Methodologies., and . IEEE Design & Test of Computers, 21 (3): 183-191 (2004)'Tis the gift to be simple.. IEEE Design & Test of Computers, 27 (2): 84-86 (2010)Power-aware global signaling strategies., , , , , and . ISCAS (1), page 604-607. IEEE, (2005)Applying VLSI EDA to energy distribution system design., , , and . ASP-DAC, page 91-96. IEEE, (2014)Guest Editors' Introduction: On-Chip Power Distribution Networks., and . IEEE Design & Test of Computers, 20 (3): 5-6 (2003)Hierarchical Multialgorithm Parallel Circuit Simulation., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (1): 45-58 (2011)A Methodology for Worst-Case Analysis of Integrated Circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 5 (1): 104-113 (1986)Simultaneous Layout Migration and Decomposition for Double Patterning Technology., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (2): 284-294 (2011)