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Disambiguation of "Montoye, Robert K."

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Testing and debugging delay faults in dynamic circuits.

, , , and . ITC, page 10. IEEE Computer Society, (2005)

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K. Stahl

K. Lindow

K. Gaiser

Grzegorz K. Karch

Robert Meissner

 

Other publications of authors with the same name

A low latency and low power dynamic Carry Save Adder., , , , , , , and . ISCAS (2), page 477-480. IEEE, (2004)An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches., , , , , , , and . J. Solid-State Circuits, 43 (4): 956-963 (2008)A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2011)Performance and power evaluation of an in-line accelerator., , , , , and . Conf. Computing Frontiers, page 81-82. ACM, (2010)A decompression core for PowerPC., , , , and . IBM Journal of Research and Development, 42 (6): 807-812 (1998)Leading-Zero Anticipator (LZA) in the IBM RISC System/6000 Floating-Point Execution Unit., and . IBM Journal of Research and Development, 34 (1): 71-77 (1990)Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor., , , , , , and . HPCA, page 423-432. IEEE Computer Society, (2012)A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI., , , , , , , and . ISSCC, page 400-401. IEEE, (2013)Design of the IBM RISC System/6000 Floating-Point Execution Unit., , and . IBM Journal of Research and Development, 34 (1): 59-70 (1990)Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure., , , , , and . ICASSP, page 2770-2774. IEEE, (2013)