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Disambiguation of "Friedman, Daniel J."

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A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.

, , , , , , , and . ISSCC, page 400-401. IEEE, (2013)

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J. K\"astner

J. Schwarz

J. K\"astner

J Walter

J. Vogel

 

Other publications of authors with the same name

VLSI sensori-motor systems., and . ICRA, page 1342-1347. IEEE Computer Society, (1991)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications., , , , , , and . ISSCC, page 94-95. IEEE, (2009)A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS., , , , and . J. Solid-State Circuits, 44 (12): 3526-3538 (2009)A semi-digital delay-locked loop using an analog-based finite state machine., , and . IEEE Trans. on Circuits and Systems, 51-II (11): 635-639 (2004)A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS., , , , , , , and . ISSCC, page 368-369. IEEE, (2009)A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator., , , , , and . ISSCC, page 458-459. IEEE, (2008)A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver., , , and . ISSCC, page 230-599. IEEE, (2007)A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI., , , , , , , and . ISSCC, page 400-401. IEEE, (2013)A linearized voltage-controlled oscillator for dual-path phase-locked loops., , and . ISCAS, page 2678-2681. IEEE, (2013)A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE., , , , , and . J. Solid-State Circuits, 42 (4): 889-896 (2007)