%0 Journal Article %1 journals/jssc/Emami-Neyestanak07 %A Emami-Neyestanak, Azita %A Varzaghani, Aida %A Bulzacchelli, John F. %A Rylyakov, Alexander V. %A Yang, Chih-Kong Ken %A Friedman, Daniel J. %D 2007 %J J. Solid-State Circuits %K dblp %N 4 %P 889-896 %T A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. %U http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#Emami-Neyestanak07 %V 42

@article{journals/jssc/Emami-Neyestanak07, added-at = {2019-07-12T00:00:00.000+0200}, author = {Emami-Neyestanak, Azita and Varzaghani, Aida and Bulzacchelli, John F. and Rylyakov, Alexander V. and Yang, Chih-Kong Ken and Friedman, Daniel J.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2ffde29921fb77ed315919b3a0e63c12d/dblp}, ee = {https://doi.org/10.1109/JSSC.2007.892156}, interhash = {d0e02b52a4b3075a563effbadcbd58f1}, intrahash = {ffde29921fb77ed315919b3a0e63c12d}, journal = {J. Solid-State Circuits}, keywords = {dblp}, number = 4, pages = {889-896}, timestamp = {2019-09-27T06:09:24.000+0200}, title = {A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc42.html#Emami-Neyestanak07}, volume = 42, year = 2007 }