Author of the publication

O for on-chip signaling in 45nm CMOS SOI.

Y. Liu, P. Hsieh, S. Kim, J. sun Seo, R. Montoye, L. Chang, J. Tierno, and D. Friedman. ISSCC, page 400-401. IEEE, (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

A. Laukemann

Jithin Jose University of Stuttgart

Basil Jose University of Stuttgart

A. Laukemann

A. Vo{\ss}

Other publications of authors with the same name

Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology.Z. Deng, S. Whiteley, T. Duzer, and J. Tierno. ASYNC, page 274-. IEEE Computer Society, (1998)Asynchronous Parallel Prefix Computation.R. Manohar, and J. Tierno. IEEE Trans. Computers, 47 (11): 1244-1252 (1998)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.A. Rylyakov, J. Tierno, H. Ainspan, J. Plouchart, J. Bulzacchelli, Z. Deniz, and D. Friedman. ISSCC, page 94-95. IEEE, (2009)An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz.M. Singh, J. Tierno, A. Rylyakov, S. Rylov, and S. Nowick. IEEE Trans. VLSI Syst., 18 (7): 1043-1056 (2010)A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.B. Sadhu, M. Ferriss, A. Natarajan, S. Yaldiz, J. Plouchart, A. Rylyakov, A. Valdes-Garcia, B. Parker, A. Babakhani, S. Reynolds and 5 other author(s). J. Solid-State Circuits, 48 (5): 1138-1150 (2013)Low-energy asynchronous memory design.J. Tierno, and A. Martin. ASYNC, page 176-185. IEEE, (1994)Asynchronous Transpose-Matrix Architectures.J. Tierno, and P. Kudva. ICCD, page 423-428. IEEE Computer Society, (1997)A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.J. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz and 5 other author(s). CICC, page 1-4. IEEE, (2012)A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS.J. Plouchart, M. Sanduleanu, Z. Deniz, T. Beukema, S. Reynolds, B. Parker, M. Beakes, J. Tierno, and D. Friedman. CICC, page 1-4. IEEE, (2012)A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology.T. Dickson, Y. Liu, S. Rylov, A. Agrawal, S. Kim, P. Hsieh, J. Bulzacchelli, M. Ferriss, H. Ainspan, A. Rylyakov and 6 other author(s). CICC, page 1-4. IEEE, (2014)

PUMA

Disambiguation of "Tierno, José A."

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.

Please choose a person to relate this publication to

A. Laukemann

Jithin Jose University of Stuttgart

Basil Jose University of Stuttgart

A. Laukemann

A. Vo{\ss}

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Tierno, José A."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.

Please choose a person to relate this publication to

A. Laukemann

Jithin Jose University of Stuttgart

Basil Jose University of Stuttgart

A. Laukemann

A. Vo{\ss}

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.