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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

J. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. Tierno, and D. Friedman. CICC, page 1-4. IEEE, (2012)

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A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology.A. Lotfy, S. Farooq, Q. Wang, S. Yaldiz, P. Mosalikanti, and N. Kurd. CICC, page 1-4. IEEE, (2015)A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.B. Sadhu, M. Ferriss, A. Natarajan, S. Yaldiz, J. Plouchart, A. Rylyakov, A. Valdes-Garcia, B. Parker, A. Babakhani, S. Reynolds and 5 other author(s). J. Solid-State Circuits, 48 (5): 1138-1150 (2013)Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study.S. Yaldiz, A. Demir, and S. Tasiran. IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (7): 1264-1277 (2008)A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.J. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz and 5 other author(s). CICC, page 1-4. IEEE, (2012)Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems.S. Yaldiz, A. Demir, S. Tasiran, P. Ienne, and Y. Leblebici. ESTIMedia, page 135-140. IEEE Computer Society, (2005)Formal verification of phase-locked loops using reachability analysis and continuization.M. Althoff, S. Yaldiz, A. Rajhans, X. Li, B. Krogh, and L. Pileggi. ICCAD, page 659-666. IEEE Computer Society, (2011)Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J. Plouchart, B. Sadhu, B. Parker and 4 other author(s). CICC, page 1-4. IEEE, (2013)Indirect phase noise sensing for self-healing voltage controlled oscillators.S. Yaldiz, V. Calayir, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, and J. Tierno. CICC, page 1-4. IEEE, (2011)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, J. Tierno, A. Babakhani, S. Yaldiz, A. Valdes-Garcia, B. Sadhu and 1 other author(s). J. Solid-State Circuits, 48 (4): 996-1008 (2013)SRAM parametric failure analysis.J. Wang, S. Yaldiz, X. Li, and L. Pileggi. DAC, page 496-501. ACM, (2009)

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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.