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Disambiguation of "Beakes, Michael P."

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A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.

, , , , , , , , , , , , , , and . CICC, page 1-4. IEEE, (2012)

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Michael P. Voigt Universität Stuttgart

P. Hommel

P. Abegglen

P. Krasteva

P. E. Bl\"ochl

 

Other publications of authors with the same name

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS., , , , , , , , , and 5 other author(s). IEEE Trans. on Circuits and Systems, 60-I (8): 2009-2017 (2013)An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 47 (4): 884-896 (2012)Errata Erratum to Ä 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"., , , , , , and . J. Solid-State Circuits, 55 (4): 1124 (2020)A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration., , , , , , , , , and . J. Solid-State Circuits, 51 (8): 1744-1755 (2016)A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS., , , , , , and . J. Solid-State Circuits, 55 (1): 19-26 (2020)A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 50 (12): 3120-3132 (2015)A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS., , , , , , , , , and 5 other author(s). CICC, page 1-4. IEEE, (2012)A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2012)A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 50 (8): 1917-1931 (2015)A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS., , , , , , , and . ISSCC, page 368-369. IEEE, (2009)