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3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation., , , , , , , and . CICC, page 663-670. IEEE, (2008)Fabrication and characterization of robust through-silicon vias for silicon-carrier applications., , , , , , and . IBM Journal of Research and Development, 52 (6): 571-581 (2008)3D chip stacking with C4 technology., , , , , , , , , and 4 other author(s). IBM Journal of Research and Development, 52 (6): 599-609 (2008)Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection., , , , , , , , , and 10 other author(s). IBM Journal of Research and Development, 49 (4-5): 725-754 (2005)Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems., , and . CICC, page 421-428. IEEE, (2007)An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 47 (4): 884-896 (2012)3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections., , , , , , , , , and 3 other author(s). IBM Journal of Research and Development, 52 (6): 611-622 (2008)An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors., , , , , , , , , and 1 other author(s). VLSIC, page 192-. IEEE, (2015)Three-dimensional silicon integration., , , , , , , , , and 6 other author(s). IBM Journal of Research and Development, 52 (6): 553-569 (2008)