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Disambiguation of "Valdes-Garcia, Alberto"

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A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.

, , , , , , , , , , , , , , and . IEEE Trans. on Circuits and Systems, 60-I (8): 2009-2017 (2013)

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Dr. Venancio Martinez Garcia University of Stuttgart

Francisco Costa Garcia University of Stuttgart

Hector Alberto Fernandez Bobadilla University of Stuttgart

Alberto Ramón Gallardo Rico University of Stuttgart

Braulio Jesús Garcia Ayala University of Stuttgart

 

Other publications of authors with the same name

Radio receiver techniques., and . CICC, page 1. IEEE, (2012)Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers., , and . CICC, page 639-642. IEEE, (2007)A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers., , , , and . VTS, page 249-254. IEEE Computer Society, (2005)Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information., , , , and . ICCAD, page 575-582. IEEE, (2015)Guest Editors' Introduction: Digitally Enhanced Wireless Transceivers., and . IEEE Design & Test of Computers, 29 (6): 5-6 (2012)Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits., , , , , , , , and . IEEE Design & Test, 31 (6): 8-18 (2014)A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS., , , , , , , , , and 5 other author(s). IEEE Trans. on Circuits and Systems, 60-I (8): 2009-2017 (2013)An On-Chip Transfer Function Characterization System for Analog Built-in Testing., , and . VTS, page 261-266. IEEE Computer Society, (2004)A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance., , and . J. Solid-State Circuits, 50 (5): 1214-1223 (2015)A Broadband CMOS Amplitude Detector for On-Chip RF Measurements., , , and . IEEE Trans. Instrumentation and Measurement, 57 (7): 1470-1477 (2008)