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Disambiguation of "Plouchart, Jean-Olivier"

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Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information.

, , , , and . ICCAD, page 575-582. IEEE, (2015)

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Jean-Noel Grad University of Stuttgart

Jean-Louis Hoslauer University of Stuttgart

Dr. Eric Jean Kervio University of Stuttgart

 

Other publications of authors with the same name

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (4): 996-1008 (2013)Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits., , , , , , , , , and 4 other author(s). IEEE Trans. on Circuits and Systems, 61-I (8): 2243-2252 (2014)An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS., , , , , , , , , and 1 other author(s). VLSIC, page 176-177. IEEE, (2012)An Integrated RF Transceiver For Short-Range, High-Speed Digital Communications in Tte U-NII 5.X GHz Band, , , , , , , , and . (1998)A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate., , , , , , , , , and 1 other author(s). ISLPED, page 434-439. ACM, (2003)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications., , , , , , and . ISSCC, page 94-95. IEEE, (2009)Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits., , , and . Proc. IEEE, 88 (10): 1572-1582 (2000)Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS., , , , , , and . ISSCC, page 542-621. IEEE, (2007)An array of 4 complementary LC-VCOs with 51.4% W-Band coverage in 32nm SOI CMOS., , , , , , and . ISSCC, page 278-279. IEEE, (2009)A cost-effective approach to a short-range, high-speed radio design in the U-NII 5.x GHz band, , , , , , , , and . Proceedings RAWCON 98 : 1998 IEEE Radio and Wireless Conference, page 133-136. Piscataway, New Jersey, IEEE, (1998)