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An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.

M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, S. Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, and D. Friedman. VLSIC, page 176-177. IEEE, (2012)

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A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance.B. Sadhu, M. Ferriss, and A. Valdes-Garcia. J. Solid-State Circuits, 50 (5): 1214-1223 (2015)Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%).B. Sadhu, and R. Harjani. ISCAS, page 1975-1978. IEEE, (2010)A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications.B. Sadhu, Y. Tousi, J. Hallin, S. Sahl, S. Reynolds, O. Renstrom, K. Sjogren, O. Haapalahti, N. Mazor, B. Bokinge and 12 other author(s). J. Solid-State Circuits, 52 (12): 3373-3391 (2017)10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs.M. Ferriss, B. Sadhu, A. Rylyakov, H. Ainspan, and D. Friedman. ISSCC, page 196-198. IEEE, (2016)Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J. Plouchart, B. Sadhu, B. Parker and 4 other author(s). CICC, page 1-4. IEEE, (2013)Modeling and synthesis of wide-band switched-resonators for VCOs.B. Sadhu, U. Omole, and R. Harjani. CICC, page 225-228. IEEE, (2008)A Fully Decoupled LC Tank VCO Topology for Amplitude Boosted Low Phase Noise Operation.B. Sadhu, T. Anand, and S. Reynolds. J. Solid-State Circuits, 53 (9): 2488-2499 (2018)Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits.J. Plouchart, F. Wang, X. Li, B. Parker, M. Sanduleanu, A. Balteanu, B. Sadhu, A. Valdes-Garcia, and D. Friedman. IEEE Design & Test, 31 (6): 8-18 (2014)A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.J. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz and 5 other author(s). IEEE Trans. on Circuits and Systems, 60-I (8): 2009-2017 (2013)A CMOS 3.3-8.4 GHz wide tuning range, low phase noise LC VCO.B. Sadhu, J. Kim, and R. Harjani. CICC, page 559-562. IEEE, (2009)

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An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.

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An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.